The present invention relates to semiconductor design technology, and more particularly, to a redundancy circuit and a fuse circuit, capable of performing various circuit operations using fuse(s).
In general, as a degree of integration of a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) device is increasing rapidly, tens of millions of memory cells are being included in one semiconductor memory device. However, even if only one of the memory cells fails, the semiconductor memory device may not perform a desired operation. As technology of fabricating the semiconductor memory device develops, a comparatively small number of memory cells may fail. Accordingly, it is very ineffective to dispose the semiconductor memory device as a defective product due the failure of only few memory cells in the product yields. In order to counter such deficiencies, redundancy memory cells are further employed in the semiconductor memory device in addition to normal memory cells. Therefore, in case where normal memory cells fail, the failed normal memory cells are replaced with the redundancy memory cells. Hereinafter, a failing memory cell that should be replaced with a redundancy memory cell is referred to as ‘a repaired memory cell’.
Herein, address information corresponding to the repaired memory cell is provided by a redundancy circuit. The redundancy circuit includes a plurality of fuses for programming the address information of the repaired memory cell. Thus, the redundancy circuit generates the address information that is programmed to the fuses, i.e., repair information, and the semiconductor memory device compares the repair information and address information that is inputted thereto in reading and writing operations, and performs an operation of accessing the redundancy memory cell instead of the repaired memory cell in case where the repaired memory cell is accessed.
For illustration purposes, a method for programming the fuses included in the redundancy circuit includes an electric cutting scheme or a laser cutting scheme. Herein, the electric cutting scheme burns out a fuse intended to be cut by applying an over current to the fuse intended to be cut and the laser cutting scheme burns out the fuse intended to be cut by blowing the fuse intended to be cut using a laser beam. In general, the laser cutting scheme is widely used than the electric cutting scheme since it is comparatively simpler than the electric cutting scheme.
Meanwhile, the fuses are generally used in the semiconductor memory device as well as in the above-described redundancy circuit. For instance, the fuses may be used to tune a voltage in a constant-voltage generating circuit sensitively operating with respect to processes and they may be used in circuits requiring fine control.
FIG. 1 illustrates a conventional fuse circuit.
Referring to FIG. 1, the fuse circuit includes a fuse block 110 and a voltage detection block 130.
The fuse block 110 includes a 0th PMOS transistor P0, a fuse F and a 0th NMOS transistor N0 that are serially connected between an external supply voltage (VDD) terminal and a ground voltage (VSS) terminal, wherein a fuse enable signal FSE is coupled to gates of the 0th PMOS transistor P0 and the 0th NMOS transistor N0. Herein, the fuse enable signal FSE transfers from a logic high to a logic low if a power-up operation of the semiconductor memory device is terminated and thus internal and external reset operations are terminated. An output node of the fuse block 110 is driven by a current flowing through a pull-up current path and a current flowing through a pull-down current path.
The voltage detection block 130 is to latch a logic level corresponding to whether the fuse F is cut or uncut, and includes a first NMOS transistor N1, a first PMOS transistor P1 and a second NMOS transistor N2. Herein, the first PMOS transistor P1 and the second NMOS transistor N2 are serially connected to each other between the VDD terminal and the VSS terminal and an output signal FSEB of the fuse block 110 is supplied to gates of the first PMOS transistor P1 and the second NMOS transistor N2. Furthermore, the first NMOS transistor N1 includes a source-drain path connected between the output node of the fuse block 110 and the VSS terminal and a gate receiving a fuse condition signal FSOP that is an output signal of the voltage detection block 130.
FIG. 2 illustrates a timing diagram for explaining an operational timing of the fuse circuit in FIG. 1.
Referring to FIGS. 1 and 2, the fuse enable signal FSE transfers from a logic high to a logic low after the internal and external reset operations are terminated, as described above.
The output signal FSEB of the fuse block 110 has different logic levels according to whether the fuse F is cut or uncut. That is, the output signal FSEB of the fuse block 110 has the logic high level in case where the fuse F is uncut and it maintains the logic low level in case where the fuse F is cut.
The fuse condition signal FSOP outputted from the voltage detection block 130 is an inverted signal of the signal FSEB outputted from the fuse block 110. In other words, the fuse condition signal FSOP becomes a logic high in case where the fuse F is cut and a logic low in case where the fuse F is uncut.
FIG. 3 illustrates a conventional redundancy circuit.
Referring to FIG. 3, the redundancy circuit includes a fuse block 310, an NMOS transistor block 330, a latch block 350, a precharge block 370 and a repair information output block 390.
The fuse block 310 is for programming address information corresponding to a repaired memory cell and includes 0th to 15th fuses F0, F1, . . . , and F15.
The NMOS transistor block 330 includes 0th to 15th NMOS transistors N0, N1, . . . , and N15 having a source-drain path connected between one of the 0th to 15th fuses F0, F1, . . . , and F15 and the VSS terminal and a gate to receive one of address information INF_ADD<0:15>. Herein, the address information INF_ADD<0:15> is in signals obtained by decoding addresses provided from the external and enabled corresponding to a corresponding memory cell matrix. For illustration purposes, the memory cell matrix (“mat”) means a group of memory cells among the plurality of memory cells, and the 0th to 15th address information INF_ADD<0:15> is activated for the memory cell mat that includes memory cells that the addresses provided externally are intended for access.
The latch block 350 latches a logic level of a node A that is driven according to the programmed 0th to 15th fuses F0, F1, . . . , and F15 and the 0th to 15th address information INF_ADD<0:15>, and includes 0th and 1st inverters INV0 and INV1.
The precharge block 370 sets an initial logic level of the latch block 350. The precharge block 370 includes a 0th PMOS transistor P0 having a source-drain path connected between the VDD terminal and the node A and a gate receives a signal WLEN transferring from a logic low to a logic high in an active operation.
The repair information output block 390 outputs a repair information signal INF_REN in response to an output signal of the latch block 350 and includes a second inverter INV2. The semiconductor memory device determines whether or not a memory cell accessed is the repaired memory cell in response to the repair information signal INF_REN.
FIG. 4 illustrates a timing diagram for explaining an operation of the conventional redundancy circuit in FIG. 3. For illustration purposes, let's assume that a ninth fuse F9 is cut, the third address information INF_ADD<3> is activated in response to a first active command ACT1 of the semiconductor memory device, and the ninth address information INF_ADD<9> is activated in response to a second active command ACT2.
Referring to FIG. 4, the node A is precharged to a logic high in response to the signal WLEN having a logic low level before the first active command ACT1 is inputted. After that, the signal WLEN transfers to a logic high in response to the first active command ACT1 and the third NMOS transistor N3 corresponding to the third address information INF_ADD<3> is turned on. Since the third fuse F3 is uncut, a current path is formed between the node A and the VSS terminal. Thus, the node A becomes a logic low and the repair information signal INF_REN becomes a logic low.
Then, the signal WLEN transfers to a logic high in response to the second active command ACT2 and the ninth NMOS transistor N9 corresponding to the ninth address information INF_ADD<9> is turned on. Since the ninth fuse F9 is cut, a current path is not formed between the node A and the VSS terminal and thus the node A maintains a logic high.
For illustration purposes, the repair information signal INF_REN having a logic high level or a logic low level means address information of the repaired memory cell.
As the semiconductor memory device is getting smaller and the degree of integration is increasing due to advancement of fabrication technology for semiconductor memory devices, accompanying parasitic capacitance is getting comparatively larger. However, since a space between lines or a space between circuits in the semiconductor memory device is being designed to be comparatively close in proportion to the increase of the integration, there occur various problems. One such a problem is a crack generated in a fuse by a fuse cutting operation.
FIG. 5 illustrates a view for explaining a crack generated in a fuse and shows a fuse intended to be cut B and other fuses A and C.
Referring to FIG. 5, the fuse B for being cut is cut through a blowing process. At this time, damage, e.g., a crack, occurs in the fuses A and C adjacent to the fuse B due to conductive by-products and an impact generated when performing the blowing process. Of course, the crack may be generated not only in the blowing process but also due to the stress between insulation layers covering fuses or a processing failure. FIG. 6 illustrates an image for showing fuses where cracks are generated.
The crack is generally classified into three types. A first one is a defective crack immediately leads to a failure of a fuse; a second one is a progressive crack, wherein a fuse having the progressive crack causes a failure according to the environment and the time; and a third one is a crack that does not cause a failure during a life of the semiconductor memory device since the crack is not serious. In the first case, since a malfunction occurs before the shipment of the semiconductor memory device and thus the crack is detected through a probe test and a package test, it is possible to repair or disuse the semiconductor memory device where the crack is generated. However, in the second case, since the crack is not detected in a test performed before the shipment of the semiconductor memory device and it causes a malfunction after the shipment of the semiconductor memory device, a user of the semiconductor memory device may be presented with a problem.
FIG. 7 illustrates a timing diagram for explaining a problem caused by a crack in the fuse F of the fuse circuit shown in FIG. 1. FIG. 7 shows the case where that the fuse F in FIG. 1 is not the fuse intended to be cut and the progressive crack is generated in the fuse F. As described in FIG. 2, in case where that the fuse F is not cut, i.e., the uncut case, the output signal FSEB of the fuse block 110 becomes a logic high and the fuse condition signal FSOP becomes a logic low. For illustration purposes, in case where the fuse F has a crack, the output signal FSEB of the fuse block 110 has a logic level that is lower than that of a normal state and becomes comparatively lower according to the environment and the time since then.
Referring to FIGS. 1 and 7, in a test performed before the shipment of the semiconductor memory device, a state of the fuse F that is not cut is reflected at the fuse condition signal FSOP and the output signal FSEB of the fuse block 110. That is, since the fuse F before the shipment has a crack but is not cut, the current flowing through a pull-up current path I_PU including the 0th PMOS transistor P0 and the fuse F becomes greater than the current flowing through a pull-down current path I_PD including the first NMOS transistor N1, and thus the output node of the fuse block 110 has a logic high level, so that the fuse condition signal FSOP becomes a logic low. Accordingly, the semiconductor memory device operates in an intended normal condition that the fuse F is not cut.
However, after the shipment of the semiconductor memory device, the fuse F having the crack is getting deteriorated according to the environment and the time and thus falls into a condition where it seems to be cut. In the status of the fuse F changes to the condition where it seems to be cut, an amount of the current flowing through the pull-up current path I_PU is getting comparatively smaller, so that a voltage level of the output node of the fuse block 110 gradually decreases. After all, since the voltage level of the output node of the fuse block 110 becomes lower than a threshold voltage level Vth by the first PMOS transistor P1 and the second NMOS transistor N2, the output node of the fuse block 110 becomes a logic low and the fuse condition signal FSOP becomes a logic high. That is, the semiconductor memory device operates undesirable due to the fuse F having the crack. However, a conventional test may not detect the fuse F having the crack as defective. For illustration purposes, as can be seen from figures, the threshold voltage level Vth is an important factor determining a transfer point of the fuse condition signal FSOP.
FIG. 8 illustrates a circuit diagram for explaining a problem caused by a crack generated in the redundancy circuit in FIG. 3. It is assumed that that the crack is generated in the 10th fuse F10. For illustration purposes, FIG. 8 shows a part of the circuit in FIG. 3 and uses the same reference numerals for the same components as those in FIG. 3. New reference numerals are used for a detailed circuit of the 0th and 1th inverters INV0 and INV1 constructing the latch block 350. Furthermore, FIG. 8 shows an example where the ninth fuse F9 in FIG. 3 is the intended fuse to be cut but a crack is generated in the 10th fuse F10. That is, the 10th fuse F10 is not a fuse intended to be cut and includes a progressive crack.
Herein, the 0th inverter INV0 includes a first NMOS transistor N1 and a first PMOS transistor P1 connected in series between the VDD terminal and the VSS terminal. The first inverter INV1 includes a second and a third NMOS transistor N2 and N3 and a second and a third PMOS transistor P2 and P3 connected in series between the VDD terminal and the VSS terminal.
FIG. 9 illustrates a timing diagram for explaining a problem caused by the crack that is generated in the 10th fuse F10 of the redundancy circuit in FIG. 8. For illustration purposes, in case where the 10th fuse F10 is not cut, the node A has a signal with a waveform of a logic low in response to the 10th address information INF_ADD<10> as in the case of using the third address information INF_ADD<3> as explained with respect to FIG. 4.
Referring to FIGS. 8 and 9, in a test before the shipment of the semiconductor memory device, the condition of the 10th fuse F10 that is not cut is reflected at the node A. That is, since the 10th fuse F10 is in the uncut condition in the test before the shipment, after the signal WLEN becomes a logic high, the current flowing through the pull-down current path I_PD including the 10th fuse F10 and the 10th NMOS transistor N10 becomes greater than the current flowing through the pull-up current path I_PU including the second and third PMOS transistors P2 and P3. Accordingly, the node A becomes a logic low and the repair information signal INF_REN becomes a logic low. In other words, the redundancy circuit operates in an intended normal condition that the 10th fuse F10 is uncut.
However, after the shipment of the semiconductor memory device, the 10th fuse F10 having the crack gets worse according to the environment and the time and thus falls into a condition where it seems to be cut. Since the condition of the 10th fuse F10 changes to the condition where it seems to be cut, an amount of the current flowing through the pull-down current path I_PD is getting comparatively smaller than that of the current flowing through the pull-up current path I_PU, where the voltage level of the node A gradually increases. After all, since the voltage level of the node A becomes greater than a threshold voltage level Vth of the 0th inverter INV0, the repair information signal INF_REN becomes a logic high. That is, the redundancy circuit is undesirably operated for the 10th fuse F10 having the crack and the repair information signal INF_REN generated thereby causes undesirable replacement of a normal memory cell with a redundancy memory cell.
As described above, a crack may be generated in a fuse by the cutting of a neighboring fuse, the processing failure, and the environment and the time, which causes undesirable operations in the typical fuse and redundancy circuits. It is preferable that the fuse where the crack is generated is detected before the shipment of the semiconductor memory device. However, since a fuse having a progressive crack that is not comparatively serious is not detected in the test before the shipment, the fuse may cause various undesirable operations after the shipment. As a result, a user may be presented with a problem and thus the reliability of a product may deteriorate.